This disclosure relates generally to the field of data processing, and in particular, to a direct memory access scheme.
In order to relieve host processors of the burden of transferring data between input/output (I/O) devices and memory as well as memory-to-memory, such operations are often accomplished by means of devices such as direct memory access (DMA) controllers and I/O controllers. DMA schemes enable I/O devices to transfer data directly to and from memory, via a system bus infrastructure, without much intervention by the host processor, as DMA controllers manage the data transfers and arbitrate access to the system bus infrastructure.
DMA schemes often employ DMA descriptors that define the source, target (i.e., destination), and size of the data transfer as well as control settings. DMA descriptors may specify an I/O device as a source or target via a reference to an I/O address or memory-mapped I/O address for the I/O device. The DMA descriptors may specify source and target memory buffers via references to scatter-gather lists that point to scattered/non-contiguous memory buffer locations/fragments. The scatter-gather lists include information such as the source memory buffer location indicating where the data is to be transferred from, target memory buffer location indicating where the data is to be transferred to, the number of bytes to be transferred, etc. Both the DMA descriptors and scatter-gather lists take the form of a one dimensional list that link other descriptors and lists sequentially.
Furthermore, transfer operations are often accompanied by encryption/decryption processing to provide data security. For example, transfer-to-target operations may include write transfers with encryption processing while transfer-from-source operations include read transfers with decryption processing. The encryption/decryption processing is typically performed by an independent cryptographic engine, separate from the DMA controller, that provides encryption and decryption services to the associated data.
However, ever-increasing data rates and the complexities associated therewith present throughput challenges for conventional DMA schemes. For example, because DMA controllers may handle simultaneous transactions for multiple I/O devices, memory buffer-to-memory buffer transfers impact the speed by which multiple transfer-with-data-processing transactions are completed. This is particularly true in communication network environments, where network protocol data rates are growing and protocol packet processing, along with associated encryption/decryption processing, becomes more complex.